The invention relates to configurable logic blocks in programmable logic devices. More particularly, the invention relates to a configurable logic block including a storage element clocked by a write strobe pulse.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1 is a simplified block diagram of a portion of a typical CLB. This structure is included, for example, in the CLBs of the Virtex(trademark) FPGAs available from Xilinx, Inc. The Virtex CLB is described in pages 3-79 through 3-82 of xe2x80x9cThe Programmable Logic Data Book 2000xe2x80x9d, published April, 2000 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
As shown in FIG. 1, a typical CLB includes a function generator FG having n data input signals F(1:n). Function generator FG is often implemented, for example, as a 4-input lookup table (where n=4) containing data stored in configuration memory cells for the PLD. Thus, the lookup table provides any function of up to 4 inputs at output terminal FCN.
In advanced FPGAs such as the Virtex FPGA, the function generator can also be programmed to function as a RAM. To provide this capability, a write strobe generator WSG is also included in the CLB. Write strobe generator WSG accepts an input clock signal CK and provides a HOLD signal and a write strobe signal WS to function generator FG. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
For example, in response to a rising edge on input clock signal CK, write strobe generator WSG drives signals HOLD and WS high, waits a sufficient time to accomplish a write to the function generator in RAM mode, brings write strobe signal WS low again, and finally brings the HOLD signal low. The HOLD signal must remain high after write strobe signal WS goes low, to prevent changes on the data input signals F(1:n) from reaching the RAM while write strobe signal WS is still active.
The typical CLB of FIG. 1 also includes another element, flip-flop FF. Flip-flop FF is a storage element that can be optionally included in the output path of the CLB. Flip-flop FF typically uses the same clock signal CK that drives write strobe generator WSG. The data input terminal IN of flip-flop FF is driven by the output signal FCN of function generator FG. The CLB output can be taken either from the flip-flop output XQ or directly from the FCN output terminal of function generator FG. Additional programmable data paths and elements are also commonly included in a CLB. These data paths and elements are not shown in FIG. 1, for clarity, but are well known in the art of PLD design.
FIG. 2 shows one implementation of flip-flop FF that is compatible with the CLB of FIG. 1. The flip-flop of FIG. 2 includes two latches (L1, L2), each including two cross-coupled inverters (203 and 204, 206 and 207, respectively). Data input signal IN is passed to latch L1 through passgate 202 when clock signal CK goes low. The data value from latch L1 is then passed to latch L2 through passgate 205 when clock signal CK goes high. Thus, in the flip-flop of FIG. 2 and given a change in the state of data input signal IN, the signal stored in latch L2 (D) changes state the next time clock signal CK changes from low to high.
Note that latched data signal D is twice inverted from data input signal IN, and thus has the same sense as that signal. Similarly, output signal OUT is twice inverted from latched data signal D (through inverters 208 and 209), and therefore also has the same sense as data input signal IN. Inverted latched data signal DB and inverted output signal OUTB have the opposite sense from data input signal IN.
There are many well-known variations on the flip-flop of FIG. 2. For example, an active-high reset signal can be added by replacing inverters 203 and 207 with 2-input NOR gates, of which the second input is the active-high reset signal. (When the reset signal goes high, the NOR output signals are forced low.) Similarly, an active-high set signal can be added by replacing inverters 204 and 206 with 2-input NOR gates, of which the second input is the active-high set signal. Active-low set and reset signals can be added by substituting 2-input NAND gates, rather than NOR gates, for the alternative inverters in each latch.
Another desirable variation involves the addition of initialization circuitry. An initialization circuit can cause the flip-flop to assume a predetermined state on receipt of an initialization signal. For example, the initialization can be performed by utilizing the set and reset circuitry previously described.
For initialization circuitry as well as with set and reset circuits, the desired result must be applied to both latches. If applied only to the first latch (e.g., L1), the output of the flip-flop is not initialized unless the clock signal CK is high. If applied only to the second latch (e.g., L2), the flip-flop only stays initialized as long as clock signal CK is low.
There are inherent drawbacks to the flip-flop of FIG. 2. One drawback is that it can be difficult to xe2x80x9ctripxe2x80x9d a latch while writing a new value to only one of the two nodes of the latch, particularly if passgate 202 is implemented as an N-channel transistor rather than a CMOS passgate. For example, to pass a new value to latch L1 of FIG. 2 (i.e., to place the new value on the output of inverter 203), the new value must overwrite an opposing value provided by the inverter. Therefore, careful circuit design is often required to successfully implement the circuit. This drawback can be overcome by placing another passgate on the feedback path (e.g., on the output of inverter 203), clocked by the inverse of the signals used to clock passgate 202. However, the addition of the new passgate for each of two latches increases the size of the flip-flop.
Another drawback to the flip-flop of FIG. 2 is not so easily overcome. The circuit is subject to several race conditions. Referring again to FIG. 2, for the circuit to function properly passgate 205 must turn off before passgate 202 turns on. However, passgate 202 should also turn off as soon as possible, to minimize the hold time of the circuit. If feedback passgates are used to make it easier to trip the latches, as described above, these passgates are also subject to race conditions.
While not a simple task, circuitry can be designed that achieves the desired result by ensuring that the correct clock signal wins the race in each instance. However, alterations to the circuit or to the circuit layout, or even to the fabrication process used to manufacture the device, can cause the race conditions to reappear and the modified flip-flop to malfunction.
This condition worsens as additional functionality is added to the flip-flop. The addition of set and/or reset circuitry and initialization capability can significantly alter the xe2x80x9cracexe2x80x9d, compounding the problems described above.
FIG. 3 shows a second well-known flip-flop that is widely used in CLBs such as that shown in FIG. 1. The flip-flop of FIG. 3 includes two latches (L3, L4), each including an AND-NOR gate (364 and 367, respectively) and an inverter (363 and 366, respectively). The AND-NOR gates and inverters are cross-coupled in each latch. Data input signal IN is passed to latch L3 through AND-NOR gate 364 when clock signal CK goes low. The data value from latch L3 is then passed to latch L4 through AND-NOR gate 367 when clock signal CK goes high. Thus, the behavior of the two flip-flops pictured in FIGS. 2 and 3 is logically the same.
The flip-flop of FIG. 3 avoids the potential problems inherent in writing to a latch through a passgate (as in FIG. 2) by replacing the passgates with AND-NOR gates. However, the flip-flop of FIG. 3 consumes more area than that of FIG. 2, and, importantly, the race conditions inherent in the flip-flop of FIG. 2 are still present in the flip-flop of FIG. 3.
Therefore, it is desirable to provide a configurable logic block for a PLD having a storage element that lacks the multiplicity of race conditions prevalent in prior art flip-flops. It is further desirable to provide a storage element that can be easily modified to include set, reset, and/or initialization functions, while minimizing the additional area and design complexity required to implement these additional functions.
The invention provides a configurable logic block for a PLD that includes a storage element having a latch circuit clocked by a write strobe pulse. The storage element uses a strobe signal already present in the CLB. Therefore, it is not necessary to design additional complicated logic to avoid race conditions in the storage element. Because the set, reset, and initialization circuitry is applied to only one latch, this functionality can be added with minimal impact on the size and complexity of the circuit. Further, because new data is written simultaneously to both nodes in the latch circuit, the data already present in the latch circuit is easily overwritten.
According to one embodiment, the invention provides a first CLB including a function generator, a write strobe generator providing a write strobe signal and an optional hold signal to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator.
In one embodiment, the storage element includes a data input terminal coupled to an optional hold circuit, which is in turn coupled to an internal node. If included, the hold circuit has a control terminal coupled to receive the hold signal from the write strobe generator. Coupled to the internal node is a data transfer circuit, which is in turn coupled to two input nodes of a latch circuit. The data transfer circuit has a control terminal responsive to the write strobe signal from the write strobe generator, and transfers data from the internal node to the latch circuit. The latch circuit has two input terminals by which it receives data from the data transfer circuit, and also two output terminals, at least one of which supplies data to an output terminal of the storage element.
In some embodiments, the latch circuit includes two cross-coupled inverters. In other embodiments, the latch circuit includes two cross-coupled logic gates other than inverters, such as NAND gates or NOR gates. A second input to each of these logic gates can be a set, reset, or initialization signal from corresponding set, reset, or initialization circuits.
Other embodiments of the invention include an output circuit coupled to one or more of the output terminals of the latch circuit, and/or a capture circuit coupled to the initialization circuit and to the data output terminal of the storage element.
In one embodiment, the initialization circuit includes a PLD configuration memory cell in which the initialization value for the storage element is stored. In other embodiments, a programmable input inversion circuit is coupled between the data input terminal and the hold circuit. The input inversion circuit can be, for example, a multiplexer programmably selecting between inverted and non-inverted versions of a signal on the data input terminal.
According to another embodiment, the invention provides a second CLB including a function generator, a write strobe generator providing a write strobe signal and an optional hold signal to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator. In this embodiment, the storage element has a data input terminal coupled to a passgate, which is in turn coupled to an input terminal of a first inverter. A gate terminal of the passgate is coupled to a hold input terminal, which is coupled to receive the hold signal from the write strobe generator. An output terminal of the first inverter is coupled to an input terminal of a second inverter. The first and second inverters drive second and first cross-coupled logic gates, respectively, through two transistors. Each of the two transistors has a gate terminal coupled to a write strobe input terminal, which is coupled to receive the write strobe signal from the write strobe generator. At least one of the two cross-coupled logic gates drives a data output terminal for the storage element.
In some embodiments, the first and second logic gates are inverters. In other embodiments, the first and second logic gates are logic gates other than inverters, such as NAND gates or NOR gates. A second input to each of these logic gates can be a set, reset, or initialization signal from corresponding set, reset, or initialization circuits.
Other embodiments of the invention include a third inverter coupled to the output terminal of one of the first and second logic gates, the third inverter driving the data output terminal of the storage element, and/or a capture circuit coupled to the initialization circuit and to the data output terminal of the storage element.
According to yet another embodiment, the invention provides a third CLB including a function generator, a write strobe generator providing a write strobe signal and an optional hold signal to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator. In this embodiment, the storage element includes: a data input terminal; an internal node; a latch circuit; optional means for passing a data input value on the data input terminal to the internal node when a signal on a hold input terminal is in a first predetermined state; and means for passing a data input value on the internal node to the latch circuit when a signal on a write strobe input terminal is in a second predetermined state.
The latch circuit has two latch input terminals and two latch output terminals. Data is passed to the two latch input terminals from the internal node by passing the data input value to a first latch input terminal and an inverse of the data input value to a second latch input terminal. At least one of the two latch output terminals drives an output terminal for the storage element.
Other embodiments include means for setting the latch circuit; means for resetting the latch circuit; means for initializing the latch circuit to a predetermined value; and/or means for capturing the predetermined value on the data output terminal of the storage element.
According to another embodiment, the invention provides a PLD including an array of configurable logic blocks (CLBs). Each CLB includes a programmable function generator, a write strobe generator, and a storage element. The write strobe generator has a write strobe output terminal and an optional hold output terminal, each of which is coupled to respective input terminals of the function generator and the storage element.